Communication systems involve a transmitter, a channel, and a receiver. Data is clocked by the transmitter and transmitted to a receiver, e.g., from a router to a hub or from one processor card to another processor card. However, the clock signal utilized to clock the data may not be transmitted with the data. One reason for not transmitting the clock signal with the data is that the clock signal induces noise to the data streams, increasing bit errors. Second, transmission of the clock signal utilizes bandwidth that could otherwise be used to transmit additional data. Third, transmitting the clock signal consumes power that is unnecessary because the receiver can reproduce the clock signal. Thus, in many applications, the clock signal is not transmitted with the data.
Even when transmitting data across a transmission medium without the corresponding clock signals, noise introduced during transmission of the data signal, such as transmitter jitter, channel jitter and data dependent jitter, reduces the sampling window for data. For example, transmitter jitter can result from many sources such as feed through, random jitter, systematic offsets and duty cycle distortion. Duty cycle distortion, for instance, is caused by non-symmetric positive and negative duty cycles of a data symbol and can show up either as a high frequency correlated jitter or as a phase step. Further, channel jitter can result from phase dispersion, such as inter-symbol interference (ISI). When a long stream of ones, for example a sinusoid of 8 MHz and 24 MHz, transitions into a long stream of zeros, for example a sinusoid of 16 MHz, differences in the propagation delay between 8 MHz, 16 MHz, and 24 MHz of the transmission medium can cause phase shifts at each transition point. The phase shifts, phase steps, and reduced duty cycles reduce the perceivable sampling window by the receiver.
When the data is transmitted without the clock signal, clocks in both the transmitter and the receiver must be coordinated to match so that data can be sampled at the center of the data sampling window. If the clocks are at substantially the same frequency, matching the clock signals is just a matter of adjusting the phase of the receiver clock to match the phase of the transmitter's clock. The phases can be matched by monitoring for a phase shift in the data.
Receivers may compensate for the smaller sampling window by attempting to align a data sampling clock signal, or recovered clock signal, with the center of the data-sampling window. More specifically, receivers typically implement a clock and data recovery (CDR) loop to track differences in phase between the data signal and sampling clock and modify the phase of the sampling clock to track the data signal. When the sampling clock is in phase with the data signal, a 90-degree phase-shift of the sampling clock will place transitions of the phase-shifted clock in the center of the sampling window.
Computations based upon sample values for bits of the data signal (typically two to four values per bit) indicate whether the phase of the sampling clock is out of sync with the phase of the data signal. For instance, assuming that the bit being sampled is a high voltage, and the prior and subsequent bits are low voltages, three sample values of the bit may be read from the data signal based upon transitions of the sampling clock. When the phase of the sample clock lags the phase of the data signal, the first two sample values read from the data signal will be a high voltage read from the bit and the next sample value will be a low voltage read from the next bit. Similarly, when the phase of the sample clock leads the phase of the data signal, the first sample value will be a low voltage read from the previous bit and the next two sample values will be a high voltage. Generally, the results are averaged over a sampling window of bits and, when, on average, the sampling clock is determined to be leading or lagging, the phase of the sampling clock is modified accordingly.
However, sometimes there is a difference between the internal frequency of the transmitter and receiver for clocking the data and that difference may vary with time, which is often referred to as spread spectrum signaling. Spread spectrum clocking is typically designed into the CDR loop to compensate for spread spectrum signaling. Spread spectrum clocking circuitry is incorporated into the design of the CDR loop to handle spread spectrum clocking. Spread spectrum clocking circuitry includes complex logic that operates at high frequencies to monitor the phase shifts in a data signal.
The complex logic and high frequency demands are dependent upon bandwidth requirements and bit error rate (BER) specifications. Bandwidth is the amount of data transmitted per unit of time and BER is the percentage of bits with errors divided by the total number of bits transmitted, received or processed per unit of time. Essentially, BER is the digital equivalent of the signal-to-noise ratio for analog systems. Thus, higher bandwidths and lower BERs require spread spectrum clocking circuitry to incorporate more complex logic and operate at higher frequencies to process data signals, especially when the data signals are spread spectrum signals. The cost of handling the spread spectrum signals is then realized in power consumption by the spread spectrum clocking circuitry and silicon area requirements for the spread spectrum clocking circuitry, neither of which can be reduced without relaxing the specifications for bandwidth, BER, or spread spectrum clocking.
Many receivers are designed for the worst case, high frequency changes that the receiver may encounter. Those receivers include CDR loops that are typically over designed for the signals that they normally encounter and, as a result, consume significantly more power than is necessary. In particular, many receivers that encounter spread spectrum signals, do not encounter the spread spectrum signals often. Thus, the additional power consumption related to the spread spectrum clocking circuitry is unnecessary most of the time, and possibly all of the time for some applications.